Verilog force release

# force : Verilog에서 신호를 특정 값으로 forcing 할 때 사용 

force module_name.signal_name = forcing_value;

 

# release : forcing 한 값을 다시 풀어줄 때 사용 

release module_name.signal_name;

 

---

[예시]

// flip-flop  

module d_flip_flop ( input clk, input rstb, input d, output q );

reg r_q;

assign q = r_q;

always @ (posedge clk or negedge rstb) 

begin

    if (!rstb) 

         r_q <= 1'b0;

    else 

         r_q <= d;

end

endmodule

 

// flip-flop Test bench

module tb_d_flip_flop();

reg clk, rstb, d;

wire q;

 

d_flip_flop u_my_flip_flop (.clk(clk), .rstb(rstb), .d(d), .q(q));

 

initial begin

    clk = 0;

    rstb = 0; 

    d = 0;

    #1000;

    force u_my_flip_flop.d = 1'b1;   // force 'd'

    #1000;

    release u_my_flip_flop.d;  // release 'd'

    #1000;

    $finish; 

end 

 

always #10 clk =~clk;

always #100 d = ~d;

 

endmodule